1. Field of the Invention
The invention relates to chip testing, and in particular to circuits and methods for testing digital logic circuit modules of an integrated circuit chip.
2. Description of the Related Art
As semiconductor techniques advance, gate counts in a chip increase rapidly. However, pins provided in a chip to test whether the integrated circuits function normally are not sufficient. Various methods and circuits have been proposed to resolve the problems of insufficient test pins.
FIG. 1 is a block diagram of a conventional boundary scan method for testing a chip. As shown, a boundary scan method is used to test modules 102, 104, 106 and 108 with several boundary scan cells 110 arranged therearound.
A conventional boundary scan method provides testing of interconnects between integrated circuits on a board without using physical test probes. It adds a boundary-scan cell, including a multiplexer and latches, to each pin on the device. Boundary-scan cells in a device can capture data from pin or core logic signals, or force data onto pins. Captured data is serially shifted out and externally compared to the expected results. Forced test data is serially shifted into the boundary-scan cells. Control is provided by a serial data path, referred to as the scan path or scan chain.
In FIG. 1, six boundary scan cells are arranged around each module. The boundary scan cells are connected in series, and receive each pattern serially. When all boundary scan cells have received test patterns, the test patterns are further sent to all modules in parallel. The test results of the modules are received in parallel. The test results are then output one by one in series.
The function of the chip module can be tested by this boundary scan method. However, as the test patterns required for all modules are received or output in series, time consumption of this operation is significant.
Moreover, the test patterns generated and modified for testing the chip must be changed when the modules of the chip change.